Memory control apparatus and method for digital signal processing

ABSTRACT

A memory control apparatus and method for digital signal processing capable of operating with a plurality of digital signal processors (DSPs) using a single memory slot and a buffer. The apparatus includes at least one DSP for processing different signals, a flash memory which can record and reproduce a digital signal, a plurality of selection switches, located on signal lines between the DSP and the flash memory, for switching input/output of signals, a three-state buffer which selectively outputs insert information of the flash memory to the DSPs according to a control signal, a control unit for providing the control signal for controlling switching of the signals, and a key input unit for determining input/output operation modes. The control unit records or reproduces the data in the flash memory according to the operation mode determined through the key input unit. The memory and the buffer are commonly used when a plurality of DSPs are operated, and thus an operation system having a simple construction is provided.

[0001] This application claims priority from the Korean PatentApplication No. 2002-0074893, filed on Nov. 28, 2002, which isincorporated in full herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a memory control apparatus andmethod for digital signal processing, and more particularly, to a systemand method for operating a plurality of digital signal processors usingone memory card.

[0004] 2. Description of the Related Art

[0005] Generally, a digital signal processor (hereinafter referred to as“DSP”) is used for real-time processing of a digital signal. The digitalsignal typically includes data representing a serial number or a digitalvalue used for indicating the corresponding analog signal. The DSP isused in diverse fields including an audio system such as a small-sizeddisc player, a radio communication system such as a cellular phone, adigital still camera (hereinafter referred to as “DSC”), and a digitalvideo camera (hereinafter referred to as “DVC”).

[0006] Recently, with the demand for combined appliances, thedevelopment of a dual appliance having two or more functions hasincreased remarkably. In particular, techniques for implementing a DVDfor taking a moving image and a DSC for recording a still image into oneappliance have been used significantly.

[0007] A technique of integrating the DSC and the DVC in the related artis illustrated in FIGS. 1 and 2. FIG. 1 is a perspective view of anapparatus for taking an image, in which a digital still camera and adigital video camera are integrated according to the related art, andFIG. 2 is a block diagram of the apparatus illustrated in FIG. 1.Referring to FIGS. 1 and 2, the body 10 of the apparatus includes a DSCsignal conversion unit 40, a DVC signal conversion unit 45, a stillimage codec unit 50, a moving image codec unit 55, a storage unit 60, aninput unit 70, a display unit 80, and a control unit 90.

[0008] A camera part 20 includes a housing 15 rotatably installed on thebody 10 within a predetermined angle, a first camera 22 for taking astill image, and a second camera 24 for taking a moving image. The firstcamera 22 and the second camera 24 are arranged to face each other.

[0009] Accordingly, the camera part 20 rotates clockwise orcounterclockwise at a predetermined angle on an rotating axis X, and itis preferable that the camera part 20 rotates to the extent that a DSClens group 22 a and a DVC lens group 24 a maintain balance with animage-taking direction A. That is, as shown in FIG. 2, it is preferablethat, if the housing 15 is manually rotated at an angle of 180° or about180°, the positions of the DSC lens group 22 a and the DVC lens group 24a change the directions in which they are facing.

[0010] The first camera 22 has a DSC lens group 22 a, a DSC driving unit22 b, a DSC detection unit 22 c, and a DSC image pickup unit 22 d. TheDSC lens group 22 a is for taking a still image, and the DSC drivingunit 22 b moves a DSC zoom lens (not illustrated) and a DSC focus lens(not illustrated) under the control of the control unit 90. The DSCdetection unit 22 c is a sensor for detecting the position of a lensunder the control of the control unit 90, and the DSC image pickup unit22 d converts the image signal of an object, which has passed throughthe DSC zoom lens (not illustrated) and the DSC focus lens (notillustrated), into an electric image signal using a charge coupleddevice or any other suitable component.

[0011] The second camera 24 also has a DVC lens group 24 a, a DVCdriving unit 24 b, a DVC detection unit 24 c, and a DVC image pickupunit 24 d, and its operation is the same as that of the first camera.

[0012] The DSC signal conversion unit 40 and the DVC signal conversionunit 45 remove noise included in electric signals output from the DSCimage pickup unit 22 d and the DVC image pickup unit 24 c, and amplifygains so that the converted electric image signals are output with aconstant or a substantially constant level. Also, the DSC signalconversion unit 40 and the DVC signal conversion unit 45 convert theelectric analog signals into digital image signals, and output automaticcontrol data through digital processing.

[0013] The still image codec unit 50, under the control of the controlunit 90, compresses the still image signal output from the DSC signalconversion unit 40 using a compression system such as JPEG. Thecompressed still image data is stored in a storage medium such as aflash memory 62 of the storage unit 60.

[0014] The moving image codec unit 55, under the control of the controlunit 90, compresses the moving image signal output from the DVC signalconversion unit 45 using a compression system such as JPEG. Thecompressed moving image data is stored in a storage medium such as atape 64 of the storage unit 60.

[0015] If a reproduction command signal for reproducing the stored imagesignal is input through the input unit 70, the still image codec unit 50and the moving image codec unit 55 discontinue the compression of thecoded data stored in the flash memory 62 and the tape 64, respectively,under the control of the control unit 90.

[0016] For example, if a reproduction command signal for reproducing thestill image signal is input through the input unit 70, the still imagecodec unit 50 discontinues the compression of the coded still image datastored in the flash memory 62, and outputs the still image data to thedisplay unit 80.

[0017] The input unit 70 has an image-taking key 70 a for providing animage-taking command signal to the control unit 90, and a plurality ofmanipulation buttons (not illustrated) for performing a plurality offunctions. The display unit 80 has a viewfinder 82 or an LCD panel 84provided in one side of the main body 10. The display unit 80 displaysthe image taken through the DSC 22 or DVC 24 or the compression-releasedimage under the control of the control unit 90.

[0018] The control unit 90 controls the entire operation of theimage-taking apparatus using various kinds of control programs stored inthe storage unit 60 and the automatic control data outputted from theDSC signal conversion unit 40 or the DVC signal conversion unit 45. Thecontrol unit 90 determines what the selected image-taking mode is by anoutput signal of a mode sensing unit 30, and drives the camera part 20corresponding to the selected image-taking mode. For example, if signalswhich indicate an on state of the DSC 22 and an off state of the DVC 24are input from the mode sensing unit 30, the control unit 90 determinesthat the image-taking mode of the camera part 20 is the still imagemode. Also, if the image-taking command signal is applied from theimage-taking key 70 a, the control unit 90 drives the DSC 22corresponding to the still image mode. If a record command signal isapplied from the input unit 70, the control unit 90 controls the stillimage codec unit 50 to compress the image signal of the object, while ifa reproduction command signal is applied, it controls the still imagecodec unit 50 to discontinue the compression of the image signal, andthen displays the image signal on the display unit 80.

[0019] As described above, the DSC and the DVC have memories for storingimage information, respectively, and in the case of integrating the twoappliances, the size of the digital camera is increased, and theoperating system for controlling the respective systems becomescomplicated.

SUMMARY OF THE INVENTION

[0020] Therefore, an object of the present invention is to provide amemory control apparatus and method for digital signal processing, andmore particularly, a system and method for operating a plurality ofdigital signal processors using one memory card.

[0021] Accordingly, an embodiment of the present invention provides amemory control apparatus and method, adapted to operate with a pluralityof digital signal processors (DSPs). The memory control apparatus andmethod employ a switch, adapted to selectively route signals for inputto the DSPs from a memory and for output from the DSPs to the memory, abuffer, adapted to selectively output to the DSPs memory informationindicating that the memory is available, and a controller, adapted tocontrol the switch to route the signals to and from the memory and DSPsand to control the buffer to selectively output the memory information.The memory is a removable memory, such as a flash memory, and the memoryinformation indicates that the memory has been inserted into a port foraccess by the memory control apparatus. The switch includes a pluralityof selection switches, coupled between the DSPs and the memory, whichare controlled by the controller. The buffer includes a three-statebuffer which selectively outputs the memory information of the memory tothe DSPs as controlled by the controller.

[0022] The apparatus and method further employ a key input unit, adaptedto indicate an operation mode, such that the control unit controlsrecording of data in the memory or reproduction of data from the memoryaccording to the operation mode indicated by the key input unit. It isalso noted that one of the DSPs is employed with a digital still cameraand another of the DSPs is employed with a digital video camera, and thecontroller controls the switch to route the signals to and from thememory and the DSPs of the digital still camera and digital videocamera.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above objects and other advantages of the present inventionwill become more apparent by describing in detail the preferredembodiments thereof with reference to the attached drawings in which:

[0024]FIG. 1 is a perspective view illustrating an apparatus for takingan image, in which a digital still camera and a digital video camera areintegrated according to the related art;

[0025]FIG. 2 is a block diagram of the apparatus illustrated in FIG. 1;

[0026]FIG. 3 is a block diagram illustrating main signal processingblocks according to an embodiment of the present invention; and

[0027]FIG. 4 is a flowchart illustrating a main signal process accordingto an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0028] A memory control apparatus and method for a digital signalprocess according to a preferred embodiment of the present inventionwill now be described in detail with reference to the annexed drawingsin which like reference numerals refer to like elements.

[0029]FIG. 3 is a block diagram illustrating main signal processingblocks according to an embodiment of the present invention. The numeralsof the general constituent elements for the digital process, which areidentical or substantially identical to those of the related art of FIG.2, and the explanation of such constituent elements will thus beomitted. In FIG. 3, the memory control apparatus for a digital signalprocess includes a signal processing unit 100 for a digital still camera(hereinafter referred to as “DSP-1”), a signal processing unit 200 for adigital video camera (hereinafter referred to as “DSP-2”), a memorystick 500, a selection switch 300, a three-state buffer 400, a key inputunit 700, and a control unit 600.

[0030] The DSP-1 100 and the DSP-2 200 process digital signals of thedigital still camera and the digital video camera, respectively. TheDSP-1 and the DSP-2 have interface units 110 and 210 for performing adigital signal input/output with the memory stick 500, and the interfaceunits 110 and 210 are respectively provided with clock terminals (SCLK)120 and 220, data terminals (SDIO) 160 and 260, enable terminals (BS)140 and 240, and insert-1 and insert-2 terminals 170 and 270 which aresignal terminals which indicate that the memory stick 500 has beeninserted.

[0031] The memory stick 500 can record or reproduce the digital signal,and has a clock terminal (SCLK), a memory stick enable terminal (BS), adata terminal (SDIO), and an insert terminal for outputting a signal forindicating that the memory stick 500 has been inserted.

[0032] Also, the memory stick 500 may be a semiconductor type flashmemory which can be installed in the signal processing apparatus, or acard type flash memory such as C.F CARD, SD CARD, SMC CARD, MMC CARD,and so on, which is detachable from the apparatus. The selection switch300 selects and connects signals input/output among the DSP-1 100, theDSP-2 200 and the memory stick 500.

[0033] The three-state buffer 400 receives the insert signal whichindicates the insertion of the memory stick 500, and outputs the insertsignal to the insert-1 and insert-2 terminals 170 and 270 under thecontrol of the control unit 600, so that the respective DSPs cancommunicate with the memory stick 500. The control unit 600 receives thekey input from the key input unit 700, and outputs a control signal 620for switching the selection switch 300 and a control signal 630 forcontrolling the three-state buffer 400. The control unit 600 alsocontrols the entire system.

[0034] The key input unit 600 is provided with a key for selecting a DSCmode and a DVC mode, and system control keys for therecording/reproducing operation. Preferably, the mode selection may beperformed through a rotary contact switch operable without a separatekey input. That is, the rotary contact switch senses the image-takingmode corresponding to the digital still camera or the digital videocamera in accordance with the rotating angle of the camera part 20 withrespect to the main body 10 as shown in FIG. 1. More preferably, itsenses the image-taking mode corresponding to the camera part 20 basedon an angle of 180° or about 180° when the camera part 20 is rotated.

[0035] An example of the operation of the memory control apparatus for adigital signal process as described above will now be explained.

[0036]FIG. 4 is a flowchart illustrating an example of the operation ofthe memory control apparatus for a digital signal process according toan embodiment of the present invention.

[0037] The control unit 600 determines whether the present mode is aread mode or a write mode through the key input unit 700 (step S10), andif it is determined that the present mode is the read mode, itdetermines whether the memory stick 500 is inserted by interpreting theinsert signal (step S11). At this time, if it is determined that thememory stick 500 is not inserted, the control unit 600 controls an OSD(On-Screen Display) unit (not illustrated) to display that the memorystick 500 is not inserted (step S12). Then, the control unit 600determines whether to select the DSP-1 mode or the DSP-2 mode throughthe key input unit 700 (step S13). If the DSP-1 mode, that is, thedigital still camera mode, is selected (step S14), the control unit 600controls the selection switch 300, so that the signals of the memorystick 500 can be connected to the respective terminals of the DSP-1.Specifically, it controls the clock terminal SCLK of the memory stick500 to be connected to the clock terminal (SCLK) 120 of the DSP-1 100,and controls outputs of the enable terminal BS and the data terminalSDIO of the memory stick to be connected to the enable terminal (BS) 140and the data terminal SDIO of the DSP-1 100, respectively. The controlunit 600 simultaneously outputs the control signal 630 for providing tothe DSP-1 100 the insert signal which indicates the insertion of thememory stick 50, and which is input to the three-state buffer 400.

[0038] Also, the control unit 600 controls the system so that the DSP-1100 reproduces the digital signal stored in the memory stick 500 anddisplays the reproduced signal on the display unit (not illustrated).

[0039] If the DSP-2 mode, that is, the digital video camera mode, isselected at step S13 (step S15), the control unit 600 controls theselection switch 300 through the same process as above, so that therespective terminal signals of the memory stick 500 are connected to therespective terminals of the DSP-2. The control unit 600 simultaneouslyoutputs the control signal 630 for providing to the DSP-2 the insertsignal which indicates the insertion of the memory stick 500, and whichis input to the three-state buffer 400. Also, the control unit 600controls the system so that the DSP-2 200 reproduces the digital signalstored in the memory stick 500 and displays the reproduced signal on thedisplay unit (not illustrated).

[0040] Alternatively, if the write mode is selected at step S10, thecontrol unit 600 determines whether the memory stick 500 is inserted byinterpreting the insert signal (step S21). At this time, if it isdetermined that the memory stick 500 is not inserted, the control unit600 controls the OSD unit (not illustrated) to display that the memorystick 500 is not inserted (step S22). Then, the control unit 600determines whether to select the DSP-1 mode or the DSP-2 mode throughthe key input unit 700 (step S23). If the DSP-1 mode, that is, thedigital still camera mode, is selected (step S24), the control unit 600controls the selection switch 300, so that the signals of the respectiveterminals of the DSP-1 can be connected to the terminals of the memorystick 500.

[0041] The control unit 600 simultaneously outputs the control signal630 to provide to the DSP-1 the insert signal indicating the insertionof the memory stick 500, which is input to the three-state buffer 400.Also, the control unit 600 controls the system so that the signalsoutput from the DSP-1 200 are stored in the memory stick 500.

[0042] If the DSP-2 mode, that is, the digital video camera mode, isselected at step S23 (step S25), the control unit 600 controls theselection switch 300 through the same process as above, so that theoutput signals of the respective terminals of the DSP-2 are connected tothe respective terminals of the memory stick 500. The control unit 600simultaneously outputs the control signal 630 for providing the insertsignal, which is input to the three-state buffer 400, to the DSP-2 200.Also, the control unit 600 controls the system so that the outputsignals of the DSP-2 200 are stored in the memory stick 500.

[0043] According to the memory control apparatus and method for digitalsignal processing of the embodiment of the present invention describedabove, the memory and the buffer are commonly used when a plurality ofDSPs are processed, and thus an operation system having a simpleconstruction is provided.

[0044] While an embodiment of the present invention has been describedin detail, it should be understood that various changes, substitutionsand alterations can be made hereto without departing from the spirit andscope of the invention as defined by the appended claims.

What is claimed is:
 1. A memory control apparatus, adapted to operatewith a plurality of digital signal processors (DSPs), the memory controlapparatus comprising: a switch, adapted to selectively route signals forinput to the DSPs from a memory and for output from the DSPs to thememory; a buffer, adapted to selectively output to the DSPs memoryinformation indicating that the memory is available; and a controller,adapted to control the switch to route the signals to and from thememory and DSPs and to control the buffer to selectively output thememory information.
 2. A memory control apparatus as claimed in claim 1,wherein: the memory is a removable memory, and the memory informationindicates that the memory has been inserted into a port for access bythe memory control apparatus.
 3. A memory control apparatus as claimedin claim 2, wherein: the memory is a flash memory.
 4. A memory controlapparatus as claimed in claim 1, wherein: the switch includes aplurality of selection switches, coupled between the DSPs and thememory, which are controlled by the controller.
 5. A memory controlapparatus as claimed in claim 1, wherein: the buffer includes athree-state buffer which selectively outputs the memory information ofthe memory to the DSPs as controlled by the controller.
 6. A memorycontrol apparatus as claimed in claim 1, further comprising: a key inputunit, adapted to indicate an operation mode; and wherein the controlunit controls recording of data in the memory or reproduction of datafrom the memory according to the operation mode indicated by the keyinput unit.
 7. A memory control apparatus as claimed in claim 1,wherein: one of the DSPs is employed with a digital still camera andanother of the DSPs is employed with a digital video camera; and whereinthe controller controls the switch to route the signals to and from thememory and the DSPs of the digital still camera and digital videocamera.
 8. A method for controlling a memory control apparatus tooperate with a plurality of digital signal processors (DSPs), the methodcomprising: controlling a switch to selectively route signals for inputto the DSPs from a memory and for output from the DSPs to the memory;and controlling a buffer to selectively output to the DSPs memoryinformation indicating that the memory is available.
 9. A method asclaimed in claim 8, wherein: the memory is a removable memory, and thememory information indicates that the memory has been inserted into aport for access by the memory control apparatus.
 10. A method as claimedin claim 9, wherein: the memory is a flash memory.
 11. A method asclaimed in claim 8, wherein: the switch includes a plurality ofselection switches, coupled between the DSPs and the memory; and theswitch controlling step includes controlling the plurality of switches.12. A method as claimed in claim 8, wherein: the buffer includes athree-state buffer; and the buffer controlling step controls thethree-state buffer to selectively output the memory information of thememory to the DSPs.
 13. A method as claimed in claim 8, furthercomprising: receiving information from a key input unit indicating anoperation mode; and controlling recording of data in the memory orreproduction of data from the memory according to the operation modeindicated by the key input unit.
 14. A method as claimed in claim 8,wherein: one of the DSPs is employed with a digital still camera andanother of the DSPs is employed with a digital video camera; and whereinthe switch controlling step controls the switch to route the signals toand from the memory and the DSPs of the digital still camera and digitalvideo camera.
 15. A computer-readable medium of instructions forcontrolling a memory control apparatus to operate with a plurality ofdigital signal processors (DSPs), the computer-readable medium ofinstructions comprising: a first set of instructions, adapted to controla switch to selectively route signals for input to the DSPs from amemory and for output from the DSPs to the memory; and a second set ofinstructions, adapted to control a buffer to selectively output to theDSPs memory information indicating that the memory is available.
 16. Acomputer-readable medium of instructions as claimed in claim 15,wherein: the memory is a removable memory, and the memory informationindicates that the memory has been inserted into a port for access bythe memory control apparatus.
 17. A computer-readable medium ofinstructions as claimed in claim 16, wherein: the memory is a flashmemory.
 18. A computer-readable medium of instructions as claimed inclaim 15, wherein: the switch includes a plurality of selectionswitches, coupled between the DSPs and the memory; and the first set ofinstructions is adapted to control the plurality of switches.
 19. Acomputer-readable medium of instructions as claimed in claim 15,wherein: the buffer includes a three-state buffer; and the second set ofinstructions is adapted to control the three-state buffer to selectivelyoutput the memory information of the memory to the DSPs.
 20. Acomputer-readable medium of instructions as claimed in claim 15, furthercomprising: a third set of instructions, adapted to control the memorycontrol apparatus to receive information from a key input unitindicating an operation mode; and a fourth set of instructions, adaptedto control the memory control apparatus to control recording of data inthe memory or reproduction of data from the memory according to theoperation mode indicated by the key input unit.
 21. A computer-readablemedium of instructions as claimed in claim 15, wherein: one of the DSPsis employed with a digital still camera and another of the DSPs isemployed with a digital video camera; and wherein the first set ofinstructions controls the switch to route the signals to and from thememory and the DSPs of the digital still camera and digital videocamera.